A MOS transistor is formed by a process including forming a polysilicon gate electrode by patterning, performing ion implantation into a silicon substrate to form extension regions, forming sidewall spacers on sidewalls of the gate electrode, performing ion implantation into the silicon substrate to form source/drain regions, forming silicide regions over the source/drain regions and the gate electrode, depositing an interlayer insulating film thereon, forming contact holes reaching the source/drain regions through the interlayer insulating film, and burying conductive plugs in the contact holes.
Concomitant with an improvement in degree of integration of integrated semiconductor devices, the degree of integration of MOS transistors per unit area is improved, and there has been improvement in microfabrication techniques. The wiring interval is decreased compared to that in the past, and positioning margin in exposure also tends to be decreased. The pitch between adjacent gate electrodes is also decreased, for example, to approximately 200 nm.
When the distance between the gate electrode and each of the conductive plugs connected to the source/drain regions is decreased, displacement of the conductive plugs may cause electrical leakage or short circuit between the gate electrode and the source/drain regions.
A process of forming silicide regions on the source/drain regions and the gate electrode is an important process for reducing electrical resistance. A top portion of the gate electrode is expanded also in a lateral direction by a silicide reaction. By this expansion, the distance between the gate electrode and each of the conductive plugs connected to the source/drain regions is decreased, and as a result, the probability of occurrence of leakage and/or short circuit increases.
In order to manufacture a microfabricated MOS transistor with high reliability, various research and development activities have been carried out, and techniques have been disclosed, for example, in Japanese Laid-Open Patent Publication Nos. 11-238879 and 2008-78403.
In a semiconductor device including a microfabricated MOS transistor, it has been desired that leakage and/or short circuit between the gate electrode and source/drain regions be suppressed.